The present invention relates to integrated circuits, and, more particularly, to a comparator.
Comparator circuits are known and a typical. comparator circuit 1 is shown in FIG. 1. The comparator circuit 1 shown in FIG. 1 includes two pairs of transistors. The first and second transistors 2 and 4 are N channel field effect transistors (FETs) and defining the first pair of transistors. The first and second transistors 2 and 4 are matched. The source of each of the first and second transistors 2 and 4 is connected to ground. The gates of the first and second transistors 2 and 4 are connected to each other by a first line 6. The drain of the first transistor 2 is connected to its gate.
The third and fourth transistors 14 and 18 are P channel FETs and define the second pair of transistors. The third and fourth transistors 14 and 18 are matched. The gate of the third transistor 14 is connected to a first voltage V1 while the gate of the fourth transistor 18 is connected to a second voltage V2. The first and second voltages V1 and V2 are to be compared. One of the first and second voltages V1 and V2 may be a reference voltage. The drain of the third transistor 14 is connected to the drain of the first transistor 2. The sources of the third and fourth transistors 14 and 18 are connected to a voltage supply Vcc or a current source.
The output of the comparator 1 is taken from an output node 20 which is between the drain of the fourth transistor 18 and the drain of the second transistor 4. The output node 20 is connected to the input of an inverter 22 or any other additional gain stages yielding a logic output. The output of the inverter 22 represents the result of the comparison. If the output of the inverter 22 is high, then the first voltage V1 is less than the second voltage V2. If the output of the inverter 22 is low, then the second voltage V2 is less than the first voltage V1.
The operation of the circuit 1 shown in FIG. 1 will now be described. The first and second voltages V1 and V2 are applied to the respective gates of the third and fourth transistors 14 and 18. The size of the voltage applied to the gates of the third and fourth transistors 14 and 18 will determine how quickly these transistors are turned on. The lower the voltage applied to the gate of the third or fourth transistor 14 or 18, the more quickly that transistor will be turned on. If the first voltage V1 is less than the second voltage V2, the third transistor 14 will be turned on more quickly than the fourth transistor 18. If the third transistor 14 is on, the drain voltage of the first transistor 2 and the gate voltages of the first and second transistors 2 and 4 will depend on how quickly the third transistor is turned on. The more quickly the third transistor 14 is turned on, the higher the voltage applied to the gates of the first and second transistors 2 and 4 and the more quickly the first and second transistors 2 and 4 are turned on. The voltage at the output node 20 will tend to be pulled low if the second transistor 4 is relatively quickly switched on in comparison to the first transistor 18. Thus, the output of the inverter 22 will be high.
If the second voltage V2 is less than the first voltage V1, the fourth transistor 18 will be switched on more quickly than the third transistor 14. If the third transistor 14 is switched on relatively slow, a lower gate voltage will be applied to the first and second transistors 2 and 4. This in turn means that the first and second transistors will be relatively slowly turned on. As the second transistor 4 is relatively slowly turned on and the fourth transistor 18 is relatively quickly turned on, the output node 20 will tend to be pulled up so that the voltage at this node will be high. Accordingly, the input to the inverter 22 will be high and thus the output of the inverter 22 will be low.
One well known use of comparators is in a Schmitt trigger. A typical Schmitt trigger is shown in FIG. 2. The principal behind a Schmitt trigger will be described in relation to FIG. 3 which shows how two voltages Vinp and Vinn vary with time. For simplicity, Vinn is a constant voltage whereas Vinp varies with time. FIG. 3 also shows the associated set and reset signals produced by the Schmitt trigger.
The Schmitt trigger is arranged to provide a set (or reset) signal each time Vinp exceeds the value of Vinn by a certain value. The Schmitt trigger provides a set signal in the example shown in FIG. 3 when Vinp exceeds Vinn by a value equal to Vthreshold1. Likewise, a reset (or set) signal is provided when Vinp is less than Vinn by a predetermined amount. In the example, the reset (or set) signal is provided when Vinp is less than Vinn by a value equal to Vthreshold2. The use of threshold values Vthreshold1 and Vthreshold2 means that it is less likely that a noisy input voltage would produce false set and/or reset signals.
FIG. 2 shows a Schmitt trigger which operates in accordance with the principals shown in FIG. 3. The Schmitt trigger includes two comparator circuits 1 of the type shown in FIG. 1. Additionally, the positive input of each comparator circuit 1 can be regarded as having a voltage source 13 and 15 respectively connected to the input. These voltage sources 13 and 15 determine the threshold value Vthreshold1 and Vthreshold2. Typically, these voltage sources 13 and 15 will take the form of a feedback circuit which connects the output of the comparator 1 to its input.
Typically a high input impedance differential Schmitt trigger requires a pair of controlled offset buffers to form these voltage sources 13 and 15. If the high input impedance or differential inputs were not required, a Schmitt trigger can be formed using a single comparator and a resistive positive feedback network.
An object of the present invention to provide a comparator which avoids or reduces the problems of the known arrangements as discussed above.
According to one aspect of the present invention, a circuit for comparing a first voltage and a second voltage includes a comparator having a current divider for dividing a bias current in accordance with the values of the first and second voltages, and for providing two currents. A current differentiation circuit receives the currents and provides an output dependent upon the difference between the currents. At least one of the current divider and current differentiation circuits weights one of the currents with respect to the other so that a given output signal is only provided when the difference between the first and second voltages exceeds an offset value. A bias generator includes a second comparator in the same configuration having the same components as the other comparator.
In this way, a comparator with an offset voltage can be provided without the need to provide the additional elements required, for example, to implement the Schmitt trigger of FIG. 2. Preferably, at least one of the current divider and current differentiation circuits includes a pair of transistors. At least one pair of transistors may not be matched to weight one of currents with respect to the other. The current differentiation circuit may include a current mirror.
Preferably the current divider includes a first pair of transistors of a first polarity or channel type, and the current differentiation circuit includes a second pair of transistors of a second polarity. Each transistor of each pair includes first and second current path terminals and a control terminal. The control terminals of the first pair of transistors are arranged to receive the first and second voltages respectively. One of the current path terminals of each of the first pair of transistors are arranged to be connected to receive a part of the biasing current, and the other of the current path terminals of the first pair of transistors are connected to one of the current path terminals of a respective one of the second pair of transistors. An output is between one transistor of the second pair and the transistor of the first pair connected to the one transistor of the second pair.
If at least one of the pairs of transistors is not matched, a given output is only provided if the difference between the first and second voltages exceeds a predetermined offset. In other words, a comparator with an offset voltage is provided without the use of feedback resistors or the like. Additionally, the comparator may have only the same number of transistors as the known comparators, but also has the offset difference between the two voltages which has to be present before a given output is provided.
Preferably, the other ones of the current path terminals of the second pair of transistors are connected to a second power supply, and the control terminals of the second pair of transistors are connected to each other and to one of the current path terminals of the other of the transistors of the second pair. Preferably, the first pair of transistors are P channel transistors and the second pair of transistors are N channel transistors. However, it is possible in embodiments of the present invention that the first pair of transistors may be N channel transistors and the second pair of transistors may be P channel transistors.
The first pair of transistors may not be matched. Alternatively, the second pair of transistors may not be matched. It is also possible in embodiments of the present invention that both of the first and second pairs of transistors are not matched. It should be appreciated that the relative sizes of the transistors in each pair allows a suitable offset value to be achieved.
Preferably, an inverter or gain stage providing a logic output is connected to the output. This is advantageous in that a digital output can be achieved from the comparator. The given output may be provided if the difference between the first and second voltages exceed the threshold, and if the difference is less than the threshold a different output may be provided.
Preferably, the bias generator includes a bias transistor, the control terminal of which is arranged to receive a bias voltage. This transistor may be regarded as being a current source. Preferably, the bias transistor is of the first polarity. The second comparator may include first and second pairs of transistors and a second bias transistor which are substantially the same and connected in the same manner as the respective first and second pairs of transistors and the bias transistor of the comparator.
Preferably, compensation circuitry is provided. The compensation circuitry may, in use, alter the voltage applied to the second bias transistor of the second comparator in response to changes in a voltage output by the first and second pairs of transistors of the second comparator. Thus, if the output of the first and second pairs of the transistors alters, then so will the voltage applied to the second bias transistor. Compensation for changes in temperature can be achieved as the transistors in the comparator part of the circuit match the transistors in the seconds comparator part of the circuit.
Preferably, the compensation circuitry is coupled to an output between one of the transistors of the first pair and one of the transistors of the second pair of transistors of the second comparator, and to the control terminal for the second bias transistor. In use, the voltage applied to the control terminal of the second bias transistor is also applied as the bias voltage to the bias transistor of the comparator. The output of the second comparator may correspond to the output of the comparator. The compensation circuit provides feedback from the output of the first and second pairs of transistors of the bias generator and the second bias transistor of the second comparator.
The compensation circuitry may include a sixth transistor which has its control terminal connected to the output of the second comparator, and a seventh transistor which has its control terminal connected to the control terminal of the second bias transistor of the bias generator. The sixth transistor may be of the first polarity and the seventh transistor may be of the second polarity. Preferably, the control terminal of the seventh transistor is connected to one of its current path terminals.
Preferably, constant voltages are arranged to be applied to the second comparator. A potential divider may be provided to provide the constant voltages. By providing constant voltages, any fluctuation in the output of the bias generator can be assumed to result from changes in temperature and/or process variations. Accordingly, the bias voltage will be varied to take into account changes in temperature so that temperature and/or process variation will not influence the output of the comparator.
A Schmitt trigger may be provided which includes at least one and preferably two comparators as described above. Preferably, the Schmitt trigger includes two comparators but only one bias generator. If a number of Schmitt triggers are required with the same detection threshold, a single bias generator can be used.